A typical optical receiver (Rx) includes at least one optoelectronic (OE) detector that detects an optical signal and converts it into an electrical current signal and at least one transimpedance amplifier (TIA) that converts the electrical current signal into an electrical voltage signal. The OE detector, which is typically a P-intrinsic-N(PIN) photodiode, produces an electrical current signal in response to light detected by it. The TIA converts this electrical current signal into an output voltage signal having some gain, commonly referred to as transimpedance gain. This output voltage signal is further processed by other circuitry of the optical Rx (e.g., a limiting amplifier (LA), clock and data recover (CDR), etc.) to recover the data signal.
In order to reduce power consumption and increase data handling capacity per channel, modem optical communication systems often have multiple single-ended Rx channels. Typically, each optical receiver (Rx) channel has a TIA circuit at its analog front-end (AFE) that converts the current signal output from the PIN photodiode into a voltage signal. The PIN photodiode capacitance at the input of the TIA circuit contributes significantly to the bandwidth of the TIA circuit. Current optical communication systems transmit data at rates of, for example, 400 gigabits per second (Gbps) or higher and have multiple Rx channels receiving, for example, 28 Gbps per channel. Hence, the TIA circuit used in such optical RXs requires more than 20 GHz to 25 GHz of bandwidth. A large PIN photodiode capacitance at the input of the TIA circuit reduces the bandwidth of the TIA circuit and therefore reduces the Rx data rate. Also, any peaking in the frequency response of the TIA circuit leads to overshoots in the transient waveform of the TIA circuit, which leads to eye closure.
Nonlinearity of the TIA circuit is also of great importance because it leads to in-band distortion components. Moreover, modern optical data transmission systems that use complex modulation schemes such as Pulse Amplitude Modulation (PAM)-4, for example, require a high level separation mismatch ratio (RLM), which is the performance metric used to quantify the linearity in a PAM-4 data eye diagram. A lower RLM value means that the amplitude of the signal being inputted into the blocks father down in the TIA chain is reduced, which results in bit errors that are not acceptable in many optical communication links.
A typical TIA circuit is shown in FIG. 1. The TIA circuit 100 includes a TIA 102, a variable feedback impedance 103 connected between an output terminal of the TIA 102 and the inverting input terminal of the TIA 102, a variable gain control amplifier (VGA) circuit 104 having an input terminal that is connected to the output terminal of the TIA 102, an output driver 105 having an input terminal that is connected to an output terminal of the VGA circuit 104, a DC offset cancellation circuit 106, and an automatic gain control (AGC) circuit 107.
A PIN photodiode 108, which is external to the TIA circuit 100, has an anode that is connected to the inverting terminal of the TIA 102 and a cathode that is connected to a Received Signal Strength Indicator (RSSI) circuit 109 and to a PIN supply voltage, VPIN. The RSSI circuit 109 is also external to the TIA circuit 100. The RSSI circuit 109 outputs an indicator signal, RSSI, which is indicative of the optical power level of the incident light striking the PIN photodiode 108. The RSSI signal is used to produce a voltage signal, VRF, which, in turn, is used to vary a variable impedance of the TIA 102, which is typically an operational amplifier (Op Amp). For ease of illustration, the variable impedance 103 of the TIA 102 is represented by a feedback resistor. The circuitry that is used to convert the RSSI signal into the voltage signal VRF is not shown.
The AGC circuit 107 receives the signals that are outputted from the VGA circuit 104 and the output driver 105 and uses them to obtain feedback signals that it then uses to adjust the gain of the amplifier stages of the VGA circuit 104 and the gain of the output driver 105. The DC cancellation circuit 106 receives the signals that are outputted from the TIA 102, the VGA circuit 104 and the output driver 105 and use them to control the gate of an N-type metal oxide semiconductor field effect transistor (NMOS) 101 and to adjust the gain of the amplifier stages of the VGA circuit 104 and of the output driver 105. The DC offset cancellation circuit 106 controls the NMOS 101 to adjust an amount of DC offset that is added to the input signal of the TIA 102.
The TIA 102 is typically a shunt feedback TIA that adjusts the variable feedback impedance 103 based on the average optical power detected by the RSSI circuit 109. One of the drawbacks of the shunt feedback TIA is that it consumes a relatively large amount of power. Another drawback is that in order to maintain the operations of the shunt feedback TIA in the linear region, the gain of the first amplifier stage 1041 of the VGA circuit 104 has to be reduced as the input optical power of the PIN photodiode 108 increases, which can result in peaking that can reduce the eye opening of the eye diagram. As indicated above, peaking is particularly problematic when complex modulation schemes, such as PAM-4, for example, are used because it degrades optical link quality, which leads to bit errors.
Accordingly, a need exists for a TIA circuit having a high bandwidth, reduced power consumption, improved linearization and reduced peaking.